FIG. 8 shows a conventional memory card circuit. In FIG. 8, reference numeral 1 designates a static RAM group, which comprises a plurality of static RAM's 2. Reference numeral 3 designates an address decoder circuit, which generates a static RAM selecting signal 13 for selecting each static RAM 2 from the static RAM group 1 by means of an address bus signal 8 and a chip enable signal 9. The static RAM group 1 is connected to a well-known chip enable signal (CE) 9, a write enable signal (WE) 10, an output enable signal (OE) 11 and a data bus signal 12. Reference numeral 14 designates a power supply input serving as an internal power supply 15 through a series diode 16. When the power supply input 14 is OFF or when a card is carried, a battery 6 supplies a current as the internal power supply 15 through a series resistor 5, for controlling the amount of current, and a protecting diode 4, for preventing reverse electric current flow, to save stored data in RAM 2. Reference numeral 7 designates an equivalent load capacitor and reference numeral 17 designates a pull-up resistor. In addition, signals E, CE, WE, and OE are "L" active signals (they are operable at "L" level).
The circuit shown in FIG. 8 is the minimum essential circuit for a memory card circuit, which is generally well-known to one skilled in the art. The address decoder circuit 3 is used in order to select each static RAM 2 from the static RAM group 1. The static RAM selecting signal 13 output from the address decoder 3 is connected to the chip select signal of the corresponding RAM 2. More specifically, this conventional memory card circuit directly outputs each terminal signal of the RAM 2 to the outside. Therefore, the operation of the circuit shown in FIG. 8 is basically the same as that of a single RAM 2.
Operation of this circuit is described hereinafter.
First, operation when there is no power supply input 14 is described. The voltage of the battery 6 is applied to the RAM 2 and the address decoder 3 through the series resistor 5 and the protecting diode 4. In addition, the RAM selecting signal 13 output from the decoder 3 is at "H" level because the resistor 17 of the chip enable signal 9 is pulled up to the internal power supply 15. Therefore, the signal 9 of each RAM 2 attains "H" level, so that the data bus signal 12 of the RAM 2 is floating. As a result, stored data in the RAM 2 can be maintained without any destruction.
Then, operation when the power supply input 14 is applied from the terminal unit is described. The power supply input 14 is input to the internal power supply 15 through the series diode 16. Generally, since a voltage of the internal power supply 15 at this time is larger than that of the battery 6, the internal power supply 15 is cut off from the battery 6 by an action of the protecting diode 4. As a result, current does not flow into the battery and no consumption occurs.
Since reading and writing of the RAM 2 is the same as that for a single RAM, a detailed description thereof is omitted and a brief description is given hereinafter. First, the address bus signal 8 is input to the decoder 3 and the RAM 2 from a terminal unit. Although the decoder 3 decodes the chip enable signal (CE) 9 of the RAM 2 corresponding to the address bus signal 8, it is actually output only when an input of the chip enable signal 9 of the decoder 3 is at "L" level. Now, it is assumed that a desired RAM 2 is selected by the decoder 3 and the chip enable signal CE of the selected RAM 2 is at "L" level. When data from the data bus signal 12 is written in a memory area of the RAM 2, the write enable signal (WE) 10 is set at "L" level while the signal CE is at "L" level. At this time, the output enable signal (OE) 11 is at "H" level. In addition, when data is read from the memory area of the RAM 2, the signal 11 is set at "L" level while the signal CE is at "L" level. At this time, the signal 10 is at "H" level. In addition, when the signal 9 is set at "H" level, the data bus signal 12 of the RAM 2 becomes floating, whereby reading or writing operation can not be performed. These operations are the same as that for a single RAM, which is well-known to one skilled in the art.
There are following problems in the conventional memory card circuit. That is,
1) The terminal signal of each RAM 2 is directly exposed (output) to the outside and when the memory card is inserted or extracted while the terminal unit is operating (the power supply input 14 is applied), the signal level becomes unstable at the connecting means between the memory card and the terminal unit (signals do not change at the same level, so that there is a short time difference at the moment that the card is inserted or extracted), causing the stored data in the RAM 2 to be destroyed.
2) When the terminal unit and the memory card are connected, if the power supply input 14 is turned OFF and the chip enable signal 9 and the write enable signal 10 are at "L" level on the side of the terminal unit, a current from the battery 6 flows into the terminal unit through the series resistor 5, the protecting diode 4 and the pull-up resistor 17, with the result that the battery 6 is discharged and consumed in a moment.
3) Since each terminal signal of the RAM 2 is basically output to the outside, resistance to static electricity of the memory card depends on the resistance to static electricity of each RAM 2.
4) The input/output impedance of the memory card when the card is carried depends on the impedance of each RAM 2 and the address decoder circuit 3, which is generally a considerably high impedance, so that resistance to static electricity or an electromagnetic field is low.
5) When the number of RAMs 2 is increased, input/output capacity of each of the signals 9 to 12 is increased, so that rising and falling time of each signal is increased and a standard value for all the RAMs 2 is not achieved, with the result that electrical performance is considerably degraded.